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Does not include information as to how microprocessor is designed or implemented Includes microprocessor instruction set, which would be the set of all assembly languages instructions. Also includes the complete set of accessible registers.:Z: #3.1 Levels of Programming LanguagesProgramming languages are divided into three categories. High level languages hide the details of the computer and operating system. Are also referred to as platform-independent. Examples include C++, Java, and Fortran "Z Z X3.1 Levels of Programming Languages (contd& )Assembly language is an example of a lower level language. Each microprocessor has its own assembly language A program written in the assembly language of one microprocessor cannot be run on a different microprocessor X3.1 Levels of Programming Languages (contd& )Backward compatibility used in order to have old programs that ran on a old microprocessor, can run on a newer model. Assembly language can manipulate the data stored in a microprocessor. Assembly language are not platform independent X3.1 Levels of Programming Languages (contd& )4Lowest level of languages are machine language. Contains binary values to cause microprocessor to perform operations. Microprocessor understands the machine language, and thus it is in this state that it executes a instruction set. High level language and assembly language are converted to machine language.55 '3.1.2 Compiling and Assembling ProgramsLHigh-level language programs are compiled Assembly languages are assembled. L M3.1.2 Compilers&Compiler checks statement in a program is valid. If every instruction is syntactically correct, then the compiler generates a object code. Linker combines object code as an executable file. Executable file copied into memory, and microprocessor then runs the machine code contained in that file''3.1.2 Compilers (contd)A high-level language statement is usually converted to a sequence of several machine code instructions. Every high-level language statement might have more then one valid conversion of a statement.  3.1.2 AssemblersEvery statement in assembly language however corresponds to one unique machine code instruction. The assembler converts source code to object code, and then the linking, and the loading of procedures occur.   Compiler vs Assembler    &3.2 A closer look at Assembly LanguageAssembly language is very important part of a instruction set architecture. Assembly instructions can be grouped together based on their functions. $ 3.2.1.1 Data Transfer InstructionsRelated with moving data from one place to another. Not be mistaken as the idea that data is literally  moved , instead it is copied from one location to another. This particular type of instruction set does not modify data. *3.2.1.1 Data Transfer Instructions (contd)Instructions related with this category perform the following transfers: Load data from memory into microprocessor. Store data from the microprocessor into memory. Move data within the microprocessor. Input data to the microprocessor. Output data from the microprocessor. 2I ZZ Z#3.2.1.2 Data Operation InstructionsAData operation instructions modify their data values. They require one or two operands, and then they store the result Arithmetic instructions make up a large part of the data operation instructions. Logic instructions perform basic logical operations on data. Shift instructions shift bits of data values in a register. $AZ ZB$3.2.1.3 Program Control InstructionszFor Assembly languages, the jump or branch instruction is commonly used to go to another part of the program. An assembly language instruction set may include instructions to call and return from subroutines. Microprocessor can also be designed to accept interrupts, which basically causes a microprocessor to stop its current process, and execute another set of instructions. {{3.2.2 Data TypesRNumeric data can be represented as integers: Unsigned integers of n-bit values can range from 0 to 2^n-1. Signed n-bit integers can have values between  2^n-1 to 2^n-1-1 - }3.2.2 Data Types (contd)UOther types include: Float: Microprocessor may have special registers only for floating point data, and its corresponding instruction set. Boolean: Instructions can perform logical operations on these values. Characters: Stored as binary values. Operations include concatenation, replacing characters, or character string manipulation. J Z@ " Z " ZA3.2.3 Addressing ModesMicroprocessor needs memory address to access data from the memory. Assembly language may use several addressing modes to accomplish this task.3.2.3 Addressing Modes (contd)3.2.3.1 Direct Mode Instruction includes memory access. CPU accesses that location in memory. Example: LDAC 5 Reads the data from memory location 5, and stores the data in the CPU s accumulator., Je 3.2.3 Addressing Modes (contd)3.2.3.2 Indirect Mode Address specified in instruction contains address where the operand resides. Example: LDAC @5 or LDAC (5) Retrieves contents of location 5, uses it to access memory address * Oa 3.2.3. Addressing Modes (contd)3.2.3.3 Register Direct and Register Indirect Modes Does not specify a memory address. Instead specifies a register. Example: LDAC R Where R is a register containing the value 5. The instruction copies the value 5 from register and into the CPU s accumulator. .4 B 3.2.3 Addressing Modes (contd)3.2.3.4 Immediate Mode The operand specified in this mode is the actual data it self. Example: LDAC #5 Moves the value 5 into the accumulator. * ?: 3.2.3 Addressing Modes (contd)3.2.3.5 Implicit Mode Does not exactly specify an operand. Instruction implicitly specifies the operand because it always applies to a specific register. Example: CLAC Clears the accumulator, and sets value to zero. No operands needed. 0 ZZV Z 3.2.3 Addressing Modes (contd)3.2.3.6 Relative Mode Operand supplied is an offset, not the actual address. Added to the contents of the CPU s program counter register to generate the required address. Example: LDAC $5 is located at memory location 10, and it takes up two blocks of memory. Thus the value retrieved for this instruction will be 12 + 5, and will be stored in the accumulator 2 ZZ Zk!3.2.3 Addressing Modes (contd)F3.2.3.7 Index Mode and Base Address Mode Address supplied by the instruction is added to the contents of an index register. Base address mode is similar except, the index register is replaced by a base address register. Example: LDAC 5(X) where X = 10 Reads data from location (5 + 10) = 15 and stores it in the accumulator. 2) ZZk ZG"3.2.3 Addressing Modes (contd)Summary a) 0: LDAC 5 (instruction gets data from location 5) 5: 10 stores value in CPU 0: LDAC @5 (instruction gets address from location 5) 5: 10 (then gets data from location 10) 10: 20 stores value in CPU c) 0: LDAC R instruction gets address from register R R: 5 stores value in CPU d) 0: LDAC R instruction gets address from register R : 5 then gets data from location 5 5: 10 stores value in CPU e) 0: LDAC # 5 stores value from instruction in CPU f) 0: LDAC (implicit) instruction gets value from stack stack stores value in CPU g) 0: LDAC $5 1: instruction adds address of next instruction (1) to 5: offset (5) to get address (6) 6: 12 stores value in CPU X _ 8 " / " _ g #3.2.4 Instruction FormatsAssembly language in machine language is represented as binary value called instruction code. Binary value for each instruction is in different format. Representation of operation to be performed is called opcode. $!3.2.4 Instruction Formats (contd)wExamples ADD = 1010 A = 00 MOVE = 1000 B = 01 LOAD = 0000 C = 10 STORE = 0001 D = 11 PUSH = 0100 POP = 1100"  o x%+3.2.4 Instruction Formats Examples (contd), A) ADD A,B,C (A=B+C) 1010 00 01 10 B) MOVE A,B (A = B) 1000 00 01 ADD A,C (A = A + C) 1010 00 10 C) LOAD B (Acc = B) 0000 01 ADD C (Acc = Acc + C) 1010 10 STORE A (A = Acc) 0001 00 D) PUSH B (Stack = B) 0101 PUSH C (Stack = C,B) 0110 ADD (Stack = B + C) 1010 POP A (A = stack) 1100 Fewer bits requires less hardware, but more instructions. Fewer bits allows faster execution.  Z('3.3 Instruction Set Architecture DesignVTo design a optimal microprocessor, the following questions and issues have to be addressed in order to come up with an optimized instruction set architecture for the CPU: Completeness; does the instruction set have all of the instructions a program needs to perform its required task. Issue of orthogonally, the concept of two instructions not overlapping, and thus not performing the same function. The amount of registers to be added. More registers enables a CPU to run faster, since it can access and store data on registers, instead of the memory, which in turn enables a CPU to run faster. Having too many registers adds unnecessary hardware. Does this processor have to be backward compatible with other microprocessors. What types and sizes of data will the microprocessor deal with? Are interrupts needed? Are conditional instructions needed?6 Z " Z)%3.4 Creating a simple Instruction SetDesigning a simple microprocessor fit for maybe a microwave will involve integrating the following models: Memory model Register model Instruction set.k , " k,* 3.4.1 Memory ModelMicroprocessor can access 64 K or 2^16 byes of memory Each byte has 8 bits or 64K x 8 of memory. I/O is treated as memory access, thus requires same instruction to access I/O as it does to access memory  +!3.4.2 RegistersThree registers in this microprocessor First register is 8-bit accumulator where the result is stored. Also provides one of the operands for instructions requiring two operands. Second register R is a 8-bit register that provides the second operands, and also stores in result so that the accumulator can gain access to it. Third register is a Z register which is 1 bit. It is either 0 or 1. If a result of a instruction is 0 then the register is set to 1 otherwise it is set to 0. $Z Z,"3.4.3 Instruction Set16 instructions, 8-bit each: Z-#3.4.3 Instruction Set (contd)xNote: LDAC uses direct addressing mode. MOVR uses the implicit addressing mode. JUMP uses immediate addressing mode. y y.$3.4.4 ImplementationB1 + 2 + & + n, or Total = 0 For I = 1 TO N do (Total = Total + I); Break Down: 1: Total = 0, I = 0 2: I = I + 1 3: Total = Total + I 4: If I n THEN GOTO 2 , >43.4.4 Implementation (contd)t CLAC Clear Accumulator STAC total Store value 0 to address total STAC i Store value 0 to address i Loop: LDAC i Load contents of address i into accumulator INAC Add 1 to the accumulator STAC i Store result from accumulator back to address i MVAC Move result from accumulator into Register R LDAC total Load Total into accumulator ADD Add contents of Register R and accumulator and store it in accumulator STAC total Store Total back to address total LDAC n Load n into accumulator SUB Subtract R (R = i) from AC (AC = n) JPNZ Loop If result is not zero then jump back to loop:u Z!t"2.0&3.4.4 Implementation (contd) 1'63.4.5 Analysis of Instruction Set, and Implementation7Cannot have value greater then 255, therefore n has to be less then or equal to 22 Is it complete? For simple hardware, maybe. Not enough to be implemented in a PC. Fairly orthogonal; however by eliminating OR and implementing by AND and NOT, we can reduce the amount of hardware used. Not enough registers.  7 82(43.5 8085 Microprocessor Instruction Set ArchitectureQProcessor has practical applications. Examples include the Sojourner robot. Contains several registers including the accumulator register, A. Other registers include B,C,D,E,H,L. Some are accessed as pairs. Pairs are not arbitrary. B and C, D and E, H and L. SP is a 16 bit stack pointer register pointing to the top of the stack. RZR3)43.5 8085 Microprocessor Instruction Set ArchitecturejContains five flags known as flag registers: Sign flag, S indicates sign of a value Zero flag, Z, tells if a arithmetic or logical instruction produced 0 for a result. Parity flag, P, is set to 1 if result contains even number of 1 s Carry flag, CY, is set when an arithmetic operation generates a carry out. "- Z Z64*43.5 8085 Microprocessor Instruction Set ArchitectureAuxiliary carry flag, generates a carry out from a lower half of a result to a upper half. Example: 0000 1111 + 0000 1000 = 0001 0111 IM register used for enable and disable interrupts, and to check pending interrupts. 4[3 V 5+)3.5.2 8085 Microprocessor Instruction Set**$Contains a total of 74 instructions.% Z%6,@3.5.2 Data movemement instruction for the 80855 microprocessor ,A & ,7- 8. 9/#3.5.2 Program control instruction $$ Z#:03.5.3. A Simple 8085 Program1: i = n, sum = 0 2: sum = sum + i, i = i - 1 3: IF i 0 then GOTO 2 4: total = sum &W 6 ;1#3.5.3 A Simple 8085 Program (contd)$$N LDA n MOV B, A XRA A Loop: ADD B DCR B JNZ Loop STA total DO Z<23.5.3 Execution trace =33.5.4 Analyzing the 8085 ISAInstruction set more complete then the simple CPU, however not sufficient enough for a PC. Able to use subroutines, and interrupts It is fairly orthogonal. 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S  6y `P  y P*    6ty `  y R*  H  0޽h ? ̙3380___PPT10.]m 0 0P$(  Pr P S >p > r P S H> `   > H P 0޽h ? f3̙fy___PPT10Y+D=' = @B +m  0 `T$(  Tr T S >BP  B r T S `9B B H T 0޽h ? f3̙fy___PPT10Y+D=' = @B +m  0 pX$(  Xr X S TFBP  B r X S GB B H X 0޽h ? f3̙fy___PPT10Y+D=' = @B +m  0 \$(  \r \ S SBP  B r \ S TB B H \ 0޽h ? f3̙fy___PPT10Y+D=' = @B +m  0 `$(  `r ` S PZBP  B r ` S ]B B H ` 0޽h ? f3̙fy___PPT10Y+D=' = @B +  0 h$(  hr h S DcBP  B r h S dB B H h 0޽h ? f3̙fh  0 l(  lr l S prBP  B x l c $HsB  B v l c 6Abd06716_ p  BH l 0޽h ? f3̙f  0 p$(  pr p S zBP  B r p S t{B B H p 0޽h ? f3̙f  0 t$(  tr t S BP  B r t S BP B H t 0޽h ? f3̙f  0 |$(  |r | S tBP  B r | S 8B B H | 0޽h ? f3̙f`  0 (  r  S B  B "  <e e H  0޽h ? f3̙f  0 $(  r  S FeP  e r  S Fe e H  0޽h ? f3̙f  0 $(  r  S KeP  e r  S xLe e H  0޽h ? f3̙f  0 $(  r  S [eP  e r  S \e e H  0޽h ? f3̙f  0 $(  r  S beP  e r  S de e H  0޽h ? f3̙f  0 $(  r  S  oeP  e r  S hse e H  0޽h ? f3̙f  0 $(  r  S HeP  e r  S  e e H  0޽h ? f3̙f[   0    (  r  S e   e   S De  e "p`PpXB @ 0D XB  0DPPpPXB @ 0D@XB  @ 0D0XB  0D p XB  @ 0DpXB  0D @XB @ 0D  XB @ 0D ` XB  0Dp @p XB  0D  XB @ 0D  P XB  0D Pp XB @ 0Dp`XB  0D`  0(e  9h) 0: LDAC 5(X) instruction gets value from index register X: 10 then adds contents of X(10) to offset (5) to get to get address (15) 15: 30 stores value in CPU 2 XB @ 0D PXB @ 0D p`XB  0D`H  0޽h ? f3̙f  0 $(  r  S eP  e r  S 4e e H  0޽h ? f3̙f  0 :(  r  S eP  e   S e e "p`PpH  0޽h ? f3̙f   0   O(  r  S eP  e   <8e ` ? 4 bits opcode   <\e 0` C2 bits Operand #1   <e0@` C2 bits Operand #2   <e@P ` C2 bits Operand #3   <e  p ? 4 bits opcode   <e  0p C2 bits Operand #1   <e 0@p C2 bits Operand #2   <e  P  ? 4 bits opcode   <e 0P  @2 bits Operand   <Le@    A4 bits Operand    S e  e "p`PpH  0޽h ? f3̙f  0 0:(  r  S gP  g   S g g "p`PpH  0޽h ? f3̙f  0 @:(  r  S gP  g   S < g "p`PpH  0޽h ? f3̙f  0 P$(  r  S #gP  g r  S t$g g H  0޽h ? f3̙f  0 `:(  r  S -gP  g   S 0g @ g "p`PpH  0޽h ? f3̙f-7  0 66pMGm6(  r  S 9gP  g r  S 9g g A5 m G #"VJrm ' <lEg?m DAC=AC ,If(AC =0) Then Z=1 Else Z=0# #  @` & <Ig?m S 0000 1111     @` % <@Xg?m MNOT   @` $ <ag? HAC=ACR,If(ACR=0) Then Z=1 Else Z=0$%    @` # <|kg? S 0000 1110     @` " <tg? MXOR   @` ! <H~g?i JAC=ACR, If(ACR=0) Then Z=1 Else Z=0$&  !  @`   <g?i S 0000 1101     @`  <g?i LOR   @`  <`g? i LAC=ACR, If(AC R=0) Then Z=1 Else Z=0$'  "  @`  <Hg? i S 0000 1100     @`  <g? i MAND   @`  <g?   V AC = 0, Z =1     @`  <g?   S 0000 1011     @`  <dg?   NCLAC   @`  <lg?e   p&AC=AC+1,If(AC+1=0) Then Z=1 Else Z = 0' '  @`  <g?e   S 0000 1010     @`  <g?e   NINAC   @`  <Lg? e  p&AC-AC-R,If(AC-R=0) Then Z=1 Else Z = 0' '  @`  <g? e  S 0000 1001     @`  <h? e  NSUB    @`  < h?   q'AC=AC+R,If (AC+R=0) Then Z=1 Else Z = 0( (  @`  <ph?   S 0000 1000     @`  <lg?   MADD   @`  <&h?a   ,IF (Z = 0) THEN GOTO G$    @`  <0h?a   l0000 0111 G$      @`   <h?a   NJPNZ   @`   <8M6MmuL(  r  S XbiP  i L - u #"J>- X <pi?he- ONO JUMP   @` W <yi?eh- LJUMP   @` V <@i?X e- LJUMP   @` U <ti?eX - LJUMP   @` T <ؔi?He- LJUMP   @` S <i?eH- Q JPNZ Loop    @` R <i?h e U AC = 0, Z = 1   @` Q <Hi? he U AC = 1, Z = 0   @` P <i?X e U AC = 2, Z = 0   @` O <i? X e U AC = 3, Z = 0   @` N <xi?H e U AC = 4, Z = 0   @` M <@i? He KSUB   @` L <i?h   NAC = 5   @` K <\i? h  NAC = 5   @` J <pi?X   NAC = 5   @` I <0i? X  NAC = 5   @` H <k?H   NAC = 5   @` G <k? H  NLDAC n   @` F <<k?h   R Total = 15    @` E < k? h  R Total = 10    @` D <)k?X   Q Total = 6    @` C <d2k? X  Q Total = 3    @` B <D;k?H   Q Total = 1    @` A <Dk? H  R STAC total    @` @ <Mk?hE   OAC = 15   @` ? <dVk?E h  OAC = 10   @` > <D_k?X E   NAC = 6   @` = <$hk?E X  NAC = 3   @` < <qk?HE   NAC = 1   @` ; <0zk?E H  KADD   @` : <k?h} E  OAC = 10   @` 9 <k?} hE  NAC = 6   @` 8 <k?X } E  NAC = 3   @` 7 <Ԟk?} X E  NAC = 1   @` 6 <(k?H} E  NAC = 0   @` 5 <|k?} HE  R LDAC total    @` 4 <k?h }  MR = 5   @` 3 <Xk? h}  MR = 4   @` 2 <k?X }  MR = 3   @` 1 <k? X }  MR = 2   @` 0 <k?H }  MR = 1   @` / <@k? H}  LMVAC   @` . <k?h  MI = 5   @` - <\k?h  MI = 4   @` , <l?X   MI = 3   @` + <|k?X  MI = 2   @` * <l?H  MI = 1   @` ) <<l?H  NSTAC I   @` ( <'l?h@ NAC = 5   @` ' <0l?@h NAC = 4   @` & <:l?X @ NAC = 3   @` % <Bl?@X  NAC = 2   @` $ <|Kl?H@ NAC = 1   @` # <m? z28 bit registers representing A, B, C, D, E, H or L3 3 @`  B0m? R R, R1, R2    @`  B)m? aIndicates memory location  @`   BTm? IM  @`   B m?  v.Indicates register pair such as BC, DE, HL, SP/ / @`   Bm?  JRP  @`   Bm? ,  z216 bit address representing address or data value.3 3 @`   Bn? ,  VG"  @`   Bn?,   I8-bit address or data value stored in memory immediately after the opcodeJ J @`  Bn?,   In  @`C  B#n? i Condition for conditional instructions. NZ (Z = 0), Z (Z = 1),P (S = 0), N (S = 1), PO (P = 0), PE (P = 1), NC (CY = 0), C (CY=1)  @`  Bx-n? i fCond  @`fB  6o ?ii`B  01 ?  `B  01 ?, , `B  01 ?  `B  01 ?`B  01 ?fB  6o ?fB  6o ?i`B  01 ?ifB  6o ?iH  0޽h ? f3̙fC5  0 44LR4(  r  S .n  n 3   R #"nbbabababbababababbababab  2 <,Kn?P  YOutput port n = A   @` 1 <xSn?P  NOUT n    @` 0 <En?P O XA = input port n   @` / <Wn?OP  LIN n   @` . <ton?P O OSP = HL   @` - <xn?P O LSPHL   @` , <n?P  hHL Stack"     @` + <|n? P  LXTHL   @` * <̍n?P K   `A, flag register = Stack   @` ) <n?K P  OPOP PSW   @`( ( <0n?P K  *rp = Stack (rp SP) ,    $  @` ' <n? P K  qPOP rp    @` & <n?P   `Stack = A, flag register   @` % <,n? P  PPUSH PSW    @`0 $ <n?P G   *Stack = rp (rp SP),    , @` # <Dn?G P  qPUSH rp   @` " <n?P G  lDE HL,     @` ! <0n? P G  LXCHG   @`   <n?P   M[rp] = A (rp = BC, DE)  $  @`  <o? P  qSTAX rp   @`  <o?P C   A = M[rp] (rp = BC, DE)  ,  @`  <o?C P  qLDAX rp   @`  <l#o?P C  z&M[G], M[G + 1] = HL"    @`  <H-o?P C  ` SHLD G"    @`  <L7o?P  z&HL = M[G], M[G + 1]"    @`  <Ao?P  ` LHLD G"    @`  <Ko?P ? dM[G] = A"     @`  <TUo??P  ^ STA G"    @`  <^o?P ? dA = M[G]"     @`  < 01 ?`B ? 01 ?C C `B @ 01 ?  `B A 01 ?  `B B 01 ?G G `B C 01 ?  `B D 01 ?  `B E 01 ?K K `B F 01 ?  `B G 01 ?`B H 01 ?OO`B I 01 ?fB J 6o ?fB K 6o ? `B L 01 ?P P fB M 6o ? H  0޽h ? f3̙f(F 0 EE d!hE(      0!p   ?3.5.2 Data operation instruction for the 80855 microprocessor 2@l( n%%D p ! #"nbopoopooopoopoopooopoopol b! <06p? 8 KAll   @` a! <?p?8  nA = A M[HL]"    @` `! <Hp?8 MANA M   @` _! <Cp? 8 KAll   @` ^! <\p? 8 pA = A r,      @` ]! <ep?8 MANA r   @` \! <np?  KAll   @` [! <\xp?  WDecimal adjust    @` Z! <p? KDAA   @` Y! <p? 4 JCY   @` X! <(p?4  v HL = HL + rp     @` W! <Єp?4 qDAD rp    @` V! <p? 4 LNone   @` U! <Hp? 4  rp = rp - 1   $ @` T! <p?4 pDCX rp   @` S! <p?  LNone   @` R! < p?   rp = rp + 1   $ @` Q! <Xp? qINX rp    @` P! <p? 0 NNot CY   @` O! <hp?0  ZM[HL] = M[HL] - 1    @` N! <p?0 MDCR M   @` M! <p? 0 NNot CY   @` L! <r? 0 R r = r - 1     @` K! <0r? 0 MDCR r   @` J! <r?   NNot CY   @` I! <"r?  YM[HL] = M[HL] + 1   @` H! <+r?   MINR M   @` G! <5r? ,   NNot CY   @` F! <\>r?,  Q r = r + 1    @` E! <`Gr?,   MINR r   @` D! <8Pr? ,  KAll   @` C! <Yr? ,  VA = A - n - CY   @` B! <(br? ,  MSBI n   @` A! <jr?   KAll   @` @! <dmr?  ZA = A - M[HL] - CY   @` ?! < fr?   MSBB M   @` >! <r? (   KAll   @` =! <r?(  VA = A - r - CY   @` u?  KAll   @` =$ <$$u?  hA = A n "     @` >$ <|Qu? MORI n   @` ?$ <lZu? m KAll   @` @$ <cu?m  nA = A M[HL]"    @` A$ <]u?m MORA M   @` B$ <Pvu? m KAll   @` C$ <u? m pA = A r,      @` D$ < u?m MORA r   @` E$ <`u?  KAll   @` F$ <Hu?  fA = A n"     @` G$ <@u? MANI n   @` H$ <u? h QFlags   @` I$ <u?h  U Operation     @` J$ <Du?h W Instruction     @`fB K$ 6o ?hh`B L$ 01 ?`B M$ 01 ?`B N$ 01 ?mm`B O$ 01 ?`B P$ 01 ?`B Q$ 01 ?qq`B R$ 01 ?`B S$ 01 ?`B T$ 01 ?vv`B U$ 01 ?""`B V$ 01 ?`B W$ 01 ?z z `B X$ 01 ?& & `B Y$ 01 ?  `B Z$ 01 ?  `B [$ 01 ?+ + `B \$ 01 ?  fB b$ 6o ?  fB c$ 6o ?h `B d$ 01 ?h `B e$ 01 ? h fB f$ 6o ?h H $ 0޽h ? f3̙f="  0 !!@2@(}!(  ( ( <u  u    @( #"J>  !( < .u?@  T Halt the CPU   @`  ( <@u?@  KHLT  @` ( <--$--@--$--B--$--E--$--G--$--H--$--J--$--L--$--N--$ --P--$ !! --Q--$!""!!--S--$"##""--U--$#$$##--V--$$%%$$--X--$%&&%%--Y--$&''&&--Z--$'((''--[--$())((--\--$)**))--]--$*++**--^--$+,,++--_--$,--,,--`--$-..----a--$.//..--b--$/11//--c--$13311--d--$35533--e--$59955--f--$9>>99--e--$>BB>>--d--$BDDBB--c--$DFFDD--b--$FHHFF--a--$HIIHH--`--$IJJII--_--$JKKJJ--^--$KLLKK--]--$LMMLL--\--$MNNMM--[--$NOONN--Z--$OPPOO--Y--$PQQPP--X--$QRRQQ--V--$RSSRR--U--$STTSS--S--$TUUTT--Q--$UVVUU--P--$VWWVV--N--$WXXWW--L--$XYYXX--J--$YZZYY--H--$Z[[ZZ--G--$[\\[[--E--$\]]\\--B--$]^^]]--@--$^__^^-->--$_``__--<--$`aa``--:--$abbaa--8--$bccbb--5--$cddcc--3--$deedd--0--$effee--.--$fggff--,--$ghhgg--*--$hiihh--'--$ijjii--%--$jkkjj--#--$kllkk--!--$lmmll----$mnnmm----$noonn----$oppoo----$pqqpp----$qrrqq----$rssrr----$sttss-- --$tuutt-- --$uvvuu----$vwwvv----$wxxww---'3--%A,(# "&*/37;?B E HKNPRS#T(U,U1U5T:S>RBPENIKLHOEQBT?U;W7X3Y/Y*Y&X"WUTQOL I EB>:51,--'3--%A,(%!       #'*.1 5 8 ; >ACEGIK!L%M(M,N0M4M7L;K>IAGDEGCIAK>M;O8P5Q1Q.R*Q'Q#P OMKIGDA > ; 740,--'3--n%5,)&#!"%'*-0358:>A!D#E&F)F,F/F2F5E8D=AA>E:G8H5I3J0J-J*J'J%I"HGEA=852/,--'3--F%!,(# "&*.269 ;#=(>,?1>5=9;<9?6A2B.C*B&A"?<951,--'3-3-82 //...///////--,,,-------++***++++++))((()))))))''&&&'''''''%%%$$%%%%%%%#########$##" " ! !!!!!""" " ! ! ! ! ! !"""""!!"""$$$$#####$$%%&&%%%%%%%''((''''''''))**))))))))+++,,+++++++---..-------////////////111111110011223333322222 4 4 4 4 44444 3 4 4!5!5"5"6!6!6!6!5!5!5!5!5#6#6#6#7#7"7"7"7"6#6#6#6%7%7%7%8%8$8$8$7$7$7%7%7'8'8'8'8'8&9&9&8&8&8'8'8)8)8)8)9)9(9(9(9(8(8)8)8*8*8+9+9+9*9*9*9*8*8*8,8,8-9-9-9,9,9,9,9,9,8,8.8.8/8/9/9.9.9.9.9.8.80808181819090909090808082727283828282828282727474747575748484847474747666666666667676757566666757585858586867675757575939393939494949494849393:2:2:2;2;2;3;3:3:3:2:2:2;0;0;0<0<1<1<1;1;1;1;0;0</</<.<.=/=/=/</</</</</<-<-<-=,=-=-=-=-<-<-<-<+<+=+=*=+=+=+=+=+=+<+<+<)<)=)=(=)=)=)=)=)=)<)<)<'<'<'<&='='='='='<'<'<';%;%<%<%<%<%<%<%<&<&;%;%;$;$:#;#;#;#;#;#;$;$;$;$9"9"9"9!:!:!:!:":":"9"9"8!8!8 8 8 9 9 9 9!8!8!7767777777755555556655533333444443311111222221100/000000--'3--~%=Z8V8S8O9L:I;G=AA?C=F<H:K9N8Q8T8X8[8^9a:d<g=i?lAnGrItLuOvSwVwZx]w`wdvgujtmrrntlviwgydza{^{[|X{T{QzNyKwHvFtCrAm=j;g:d9`8]8Z8--'3--f%1Z=W=T>Q>N?JBEEBI?M>P>R=U=X=Z>]>_?bBfEjJmNpQqTqWrZr\r_qbqepimnjqftbu_u]vZvXvUuRuPtMqInEiBe?b>_>\=Z=--'3--F%!ZCUCQDMFIIGLEOCSCXC\E`GcIfMiQkUlZm^lbkfijflco`p\pXpSoOlLjIfFbD^CZC--'3--F%!ZHVHSIPKMMKOJRITHXI[J^K`MbPdSfVgZg]g`fcdfbh`i^k[kXkTiRhOfMcK`I]HZH--'3--u8% [M[M[M[M[L[L[L\L\M\M[M[MYMYMYMYMYLYLYLZMZMYMYMWMWMWMWMWLWLWLXLXMXMWMWMUNUNUMUMUMVMVNUNUNTOTOSOSNSNSNSNTNTNTNTOTORPRPRPQOQOQOQORORORORPRPPQPQPQPPPPPPPPPPPQPQORORORNRNQNQOQOQORORORNTNTNTNTMTMSMSNSNSNTNTMUMUMVMVMUMUMUMUMUMUMUMWMWMXMXLXLWLWMWMWMWMWMWMYMYMZMZMZLYLYMYMYMYMYMYN[N[N\M\M[M[M[M[N[N[N[O]O]O]O]N]N]N]N]N]O\O]O]P^P^P_P_O_O_O^P^P^Q_Q_R`R`Q`Q`Q`Q`Q`Q_Q_Q_S`S`SaSaSaSaSaRaRaS`S`S`UaUaUbUbUbUbTbTaUaUaWbWbWbWbWcVcVcVcVbVbWbWbYbYbYbYcYcYcYcXcXbXbYbYbZbZb[b[b[c[c[cZcZbZbZb\b\b]b]b]c]c]c\c\b\b\b\b^a^a_a_b_b_b_b^b^b^b^a^a``````aaaa`a`a`a`a`a````b_b_b_b`b`b`b`b`b`a`b_b_c^c^c^d^d_d_d_c_c_c^c^d]d]e\e]e]e]e]e]d]d]d]d]e[e[e[f[f[f[f[e\e[e[e[fYfYfYfYgYgYgYgZfZfYfYfWfWfWfWgWgWgWgXfXfXfWfWfVfVfUfUfUgUgUgVfVfVfVfVeTeTeSeSfSfSfSfTeTeTeTdRdRdRdQeQeReReReRdRdRdRcQcQcPcPdPdPcQcQcQcQaPaPaOaOaObObObObObPaPaP`O`O_N_N`N`N`N`N`N`O`O`O^N^N^N^M^M^M^M^M^M^N^N^N--'3--%Atpmieb_\ Y WUSQPON#N&N*O-P1Q4S7U:W=Y@\B_DbFeGiImIpJtJxJ|IIGFDB@=:741-*&# |xt--'3--v%9tq n k h e b ^ZXWVU U#T&U)U,V/W2X4Z7^;b?e@hBkCnCqDtDwD{C~CB@?;742/,)&#  ~ { w t--'3--N%%tojfb_][![$[&[)[+]/_3b7f:j<o=t>y=~<:73/+)&$!~yt--'3--F%!tpmigdba#a&a*b-d0g3i5m6p7t8x7|6530-*&#|xt--'3--8* vvvvvvvwwvvvttttttttuttrrrrrrrrssrrppppppppqqppnnnnnnnnoonnmmlllllmmmmmkkkjjkkkkkkkjjiiiiiijjjjh h h h h h h hhi h h g"g"g"g"g!g!g!g!g"g"g$g$g$f$f$f#f#f#g#g#g$g$g%g%f&f&f&f%f%f%f%f%g%g%g'g'f(f(f(f'f'f'f'g'g'g)g)g*g*f*f)f)f)f)g)g)g)h+h+g,g,g+g+g+g+g+h+h+i-i-i-h-h-h-h-h-h,h,i-i-j.j.j/j/i/i/i.j.j.k/k/l0k0k0k0k0k0k/k/k/k/m0m0m1m1m1l1l1l1l1m0m0m0o1o1o1o2o2n2n2n2n1n1o1o1q2q2q2q2q3p3p3p2p2p2q2q2r2r2s2s3r3r3r3r2r2r2r2t2t2u2u3u3t3t3t3t3t2t2t2v2v2w2w2w3v3v3v3v3v2v2v2x2x2y2y2y2x3x3x3x2x2x2x2z1z1z1{1{2z2z2z2z2z1z1z1|0|0|0}0|1|1|1|1|0|0|0}/}/~/~/~0~0~0~0}0}/}/}/.....////...,,,,------,,+++*+++++++)))))))**)))''''''''('''%%%%%%%%&&%%#######$$##""!!!!!!""""  ~}}}}}~~~~~}}||{{||||||||zzyzzzzzzzzzxxxxxxxxyxxx--'3--8 ,+*-*-)-)-),+*,*,*,*,+,+(0&3&3%3%2'0'/(/(0(0(0$6"8"8!8!8!8#5#5$5$5$6$6 ;>>>>=;;; ; ; ;ADDCCA@@AAAGIIIIIFFFFGGLOOOONLLLLLR T U U T TQQQRRR X Z ZZZZ W W W W X X]````_]]]]]]cefeeebbbccc--'3--8 t&v(v(v)v)u)s's&s&t&t&t&y+{-{.{.z.z.x,x+x+y+y+}023333}1}0}0}0}058888865555;===>=;;::;;@BCC@@@@@@EGGHHHFEEEEEJLMMMMKJJJJJOQRRRRPPOOOTVVWWUTTTT--'3--%YV`--'@Times New Roman-. 2 6= Chapter 3."System7-@Times New Roman-. 32 K'Instruction Set ArchitecturesC.-՜.+,0@     On-screen ShowPSC5 8Times New RomanSymbolRadar Chapter 3Instruction Set Architecture$3.1 Levels of Programming Languages-3.1 Levels of Programming Languages (contd)-3.1 Levels of Programming Languages (contd)-3.1 Levels of Programming Languages (contd)(3.1.2 Compiling and Assembling Programs3.1.2 Compilers3.1.2 Compilers (contd)3.1.2 AssemblersCompiler vs Assembler'3.2 A closer look at Assembly Language% 3.2.1.1 Data Transfer Instructions+3.2.1.1 Data Transfer Instructions (contd)$3.2.1.2 Data Operation Instructions%3.2.1.3 Program Control Instructions3.2.2 Data Types3.2.2 Data Types (contd)3.2.3 Addressing Modes3.2.3 Addressing Modes (contd)3.2.3 Addressing Modes (contd) 3.2.3. Addressing Modes (contd)3.2.3 Addressing Modes (contd)3.2.3 Addressing Modes (contd)3.2.3 Addressing Modes (contd)3.2.3 Addressing Modes (contd)3.2.3 Addressing Modes (contd)3.2.4 Instruction Formats"3.2.4 Instruction Formats (contd),3.2.4 Instruction Formats Examples (contd)(3.3 Instruction Set Architecture Design&3.4 Creating a simple Instruction Set3.4.1 Memory Model3.4.2 Registers3.4.3 Instruction Set3.4.3 Instruction Set (contd)3.4.4 Implementation3.4.4 Implementation (contd)3.4.4 Implementation (contd)73.4.5 Analysis of Instruction Set, and Implementation53.5 8085 Microprocessor Instruction Set Architecture53.5 8085 Microprocessor Instruction Set Architecture53.5 8085 Microprocessor Instruction Set Architecture*3.5.2 8085 Microprocessor Instruction Set Slide 45 Slide 46 Slide 47 Slide 483.5.3. A Simple 8085 Program$3.5.3 A Simple 8085 Program (contd)3.5.3 Execution trace3.5.4 Analyzing the 8085 ISA Designed & Developed By (Harman Jit Singh) KANWER ACADEMY 98, New Model Town, Ludhiana Contact No:- 98880-03277 E-Mail:- singh_harmanjit@yahoo.com  Fonts UsedDesign Template Slide Titles5Root EntrydO)jbPictures8Current UserDSummaryInformation(kP$_Z GuruRamDassGGuruRamDassG Singh  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijlmnopqrstuvwxyz{|}~Root EntrydO)Pictures8Current UserSummaryInformation(kPPowerPoint Document(~DocumentSummaryInformation8